Registered FSM Outputs

High-speed digital designs often fail timing closure when FSM state registers drive complex combinational output logic. Registering the FSM outputs cuts this combinational path in half, allowing the circuit to run at higher clock frequencies. However, a naive implementation of a registered output delays all signals by one clock cycle, which can break downstream protocol timing.

The sequence_detector module searches for the overlapping bit pattern 110 on the serial din input. When the pattern is detected, the match output must be asserted for exactly one clock cycle. Crucially, the match signal must be driven directly by a flip-flop, but it must appear on the exact same clock cycle as it would in a standard combinational-output Moore machine. This requires computing the output register's D-input based on the next-state transition rather than the current state.

Timing and Reset Rules

• Clock edge: posedge clk
• Reset type: Synchronous
• Reset polarity: Active-low (rst_n)
• Output values on reset: match goes to 0, internal state resets to IDLE
• Overlap: The pattern can overlap (e.g., 1110 results in a match on the final zero)
• Output constraint: match must be a registered output (driven by a flip-flop)
• Timing constraint: match must assert one cycle after the final bit of the sequence is sampled

Worked Trace

Cycle 1: rst_n=0, din=0 → match=0 (state=S_IDLE) Cycle 2: rst_n=1, din=1 → match=0 (state=S_1) Cycle 3: rst_n=1, din=1 → match=0 (state=S_11) Cycle 4: rst_n=1, din=0 → match=1 (state=S_110 is active, lookahead logic drove match high) Cycle 5: rst_n=1, din=0 → match=0 (state=S_IDLE) Cycle 6: rst_n=1, din=1 → match=0 (state=S_1)

State Diagram

flowchart LR
    RESET(( )) -->|reset| S_IDLE
    S_IDLE((S_IDLE)) -->|din=1| S_1
    S_IDLE -->|din=0| S_IDLE
    S_1((S_1)) -->|din=1| S_11
    S_1 -->|din=0| S_IDLE
    S_11((S_11)) -->|din=0| S_110
    S_11 -->|din=1| S_11
    S_110(["S_110 ★"]):::out -->|din=1| S_1
    S_110 -->|din=0| S_IDLE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

Timing Diagram

{ "signal": [
  { "name": "clk",   "wave": "p........." },
  { "name": "rst_n", "wave": "01........" },
  { "name": "din",   "wave": "x1.0..1..0" },
  {},
  { "name": "match", "wave": "0...10...1" }
], "head": { "text": "Pattern 110 detected twice, match asserts exactly one cycle after the final bit." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; all registers go to 0 when asserted | | din | input | 1 | Serial data input | | match | output | 1 | Registered output; asserts for one cycle when 110 is detected |

Constraints

• The match output must be a registered output, meaning it is assigned within an always @(posedge clk) block.
• The timing of match must be identical to a standard Moore machine (asserts one cycle after the final bit of the sequence is sampled).
• The reset is synchronous and active-low.

Topics

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