Replication with Parameterized Count
Datapaths often need to route signals of varying widths to functional units, requiring dynamic sign extension based on target bus sizes. Hardcoding the number of replicated sign bits prevents a module from scaling across different architectural configurations. A robust arithmetic logic unit or bus interface relies on parameterized sign extension to ensure the MSB is correctly duplicated regardless of the input and output bus widths.
This module performs sign extension on an input vector to produce a wider output vector. The number of bits to replicate is determined dynamically by the difference between the parameterized output width and the input width. The most significant bit (MSB) of the input is replicated the required number of times and concatenated with the original input vector to form the final output.
| Parameter | Default | Description | |-------------|---------|-------------| | IN_WIDTH | 8 | Bit width of the input vector | | OUT_WIDTH | 16 | Bit width of the output vector |
| Signal | Direction | Width | Description | |--------|-----------|-------------------|-------------| | in | input | IN_WIDTH bits | The input vector to be sign-extended | | out | output | OUT_WIDTH bits | The sign-extended output vector |
Constraints
- The design must be purely combinational; no clock or reset ports are used.
- You must use the replication operator
{N{bit}}where the multiplierNis dynamically derived from the module parameters. OUT_WIDTHis guaranteed to be strictly greater thanIN_WIDTH.
Topics
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