Retiming and Register Balancing
High-speed DSP pipelines often compute sum-of-products operations. A naive RTL implementation computing y = (a * c) + (b * c) combinationally and registering the result requires two parallel multipliers. This creates a severely unbalanced pipeline where the first stage is extremely slow and consumes excessive area, while the subsequent stages are mostly idle. Synthesizers can sometimes retime logic automatically, but writing explicitly balanced RTL guarantees high-frequency operation.
The module computes the operation y = (a * c) + (b * c). Instead of using two multipliers, you must re-architect the datapath to use only a single multiplier. Compute the sum of a and b in the first stage, register this intermediate sum along with c, and perform the multiplication by c in the second stage. The final output y must also be registered.
- Clock edge:
posedge clk - Reset: Asynchronous active-low
rst_n - Output values on reset: All pipeline registers and the final output
ymust asynchronously reset to 0.
Worked Trace
Cycle 1: rst_n=0 → sum_reg=0, c_reg=0, y=0 Cycle 2: rst_n=1, a=2, b=3, c=4 → sum_reg=5, c_reg=4, y=0 Cycle 3: rst_n=1, a=1, b=1, c=2 → sum_reg=2, c_reg=2, y=20 Cycle 4: rst_n=1, a=5, b=5, c=5 → sum_reg=10, c_reg=5, y=4
Timing Diagram
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "a", "wave": "x=====.", "data": ["2", "1", "5", "10", "0"] },
{ "name": "b", "wave": "x=====.", "data": ["3", "1", "5", "20", "0"] },
{ "name": "c", "wave": "x=====.", "data": ["4", "2", "5", "2", "0"] },
{},
{ "name": "y", "wave": "===.=.=", "data": ["0", "20", "4", "50"] }
], "head": { "text": "Pipeline latency of 2 clock cycles." } }Port Table
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all registers go to 0 when asserted | | a | input | 8 | First operand | | b | input | 8 | Second operand | | c | input | 8 | Multiplier operand | | y | output | 17 | Pipelined result of (a * c) + (b * c) |
Constraints
- Clock edge must be
posedge clk. - Reset must be asynchronous, active-low, and clear all registers to 0.
- The module must have exactly two pipeline stages (a latency of 2 clock cycles).
- The bit width of the intermediate sum must be 9 bits to prevent overflow.
- The final output
ymust be 17 bits and must be driven directly by a register. - You must use exactly one multiplication operator in your RTL to balance the logic.
Topics
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