2-to-1 Multiplexer
Design a 2-to-1 multiplexer in Verilog.
A multiplexer selects one of its data inputs and forwards it to the output based on a select signal.
Truth Table
| sel | y | |-----|-------| | 0 | a | | 1 | b |
When sel = 0, output y equals input a. When sel = 1, output y equals input b.
This is the most fundamental routing element in combinational digital design and appears inside nearly every complex circuit.
Constraints
- Pure combinational logic — no sequential elements
- Implement using a single continuous assignment (
assign) - No always blocks required
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.