Scan Capture Cycle Analysis
Structural testing relies on scan chains to observe and control internal flip-flops during manufacturing test. The circuit below contains three scan flip-flops (FF1, FF2, FF3) with outputs Q1, Q2, and Q3. The combinational logic driving the functional data inputs is defined as D1 = Q2 AND Q3, D2 = PI, and D3 = Q1 XOR Q2.
The scan chain is fully loaded with the vector Q1 = 1, Q2 = 0, and Q3 = 1. The primary input PI is held at 1. The scan enable signal SE is driven to 0 for exactly one clock cycle to perform a functional capture.
Determine the new state of the flip-flops after this capture cycle and analyze the fault coverage implications.
Constraints
- Assume zero hold time violations and ideal clock routing.
- All flip-flops are positive edge-triggered.
- The scan chain shift order is
Scan_In→FF1→FF2→FF3→Scan_Out.
Topics
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