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Codiode/Problems/Combinational Logic

Sign Extension

MediumLogic CircuitAnalyze

Narrow data signals must frequently cross into wider buses inside ALUs and memory interfaces.

A 4-bit two's complement signal X holds the binary value 1101. This signal must be extended to an 8-bit bus Y before an arithmetic operation can take place. Two extension methods are proposed: zero-padding the most significant bits and replicating the sign bit.

Evaluate both extension methods and determine the resulting decimal values to verify the correct hardware implementation for two's complement arithmetic.

Constraints

  • All binary numbers must be evaluated as two's complement signed integers.
  • The original signal X is strictly 4 bits wide.
  • The target bus Y is strictly 8 bits wide.

Topics

arithmetictwos-complementdata-typesrtl-bugs

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