Signed Port Declarations
Digital signal processing pipelines frequently pass signed data between arithmetic blocks. When crossing module boundaries, Verilog requires explicit sign declarations on ports. If an input port carrying negative values is declared without the signed keyword, the compiler silently treats the data as unsigned, causing operations like arithmetic right shifts to pad with zeros instead of sign-extending.
This module computes an arithmetic right shift on an 8-bit signed input. The input value a is shifted right by a specified 3-bit amount shamt. Because the input represents a signed two's complement integer, the shift operation must duplicate the sign bit (the most significant bit) into the newly vacated upper bits to preserve the negative value.
This circuit is purely combinational. There is no clock or reset. The output y must update immediately whenever a or shamt changes.
Example Evaluation Trace: • Input: a = 8'b10011100 (-100), shamt = 2 → Output: y = 8'b11100111 (-25) • Input: a = 8'b01111111 (127), shamt = 3 → Output: y = 8'b00001111 (15)
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Signed data input | | shamt | input | 3 | Unsigned shift amount | | y | output | 8 | Signed data output |
Constraints
- The module must be purely combinational.
- The
aandyports must explicitly use thesignedkeyword in their declarations. - The arithmetic right shift must be implemented using the
>>>operator. - Negative values on
amust retain their sign bit during the shift.
Topics
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