System Level Debug: The Integration Failure
A system controller integrates a sequence detector FSM with a datapath register to capture incoming data upon detecting a specific preamble.
Expected behavior: The FSM asserts the Match signal when the input sequence 1011 is detected on Seq_In. The datapath register must capture the value of Data_Bus on the exact clock cycle that Match goes high.
System-level simulation shows a timing mismatch. When the sequence 1011 is applied, the Match signal goes high correctly, but the register latches the value of Data_Bus one clock cycle too late. The output Captured_Data reflects the data bus state from the cycle after the match instead of the match cycle. Inspect the circuit and correct the fault.
Constraints
- Do not modify the internal logic of the sequence detector FSM or the datapath register.
- Fix the synchronization issue using exactly one additional sequential element.
- Only modify the interface routing between the two submodules.
Topics
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