SystemVerilog Enum Default Encoding
Synthesizers assign arbitrary binary values to uninitialized enumerated types during state machine inference. The provided netlist shows a finite state machine using an enumerated type state_t with states IDLE, READ, PROCESS, and WRITE. No explicit binary assignments are provided in the RTL. The synthesis tool has mapped these logical states to a physical register state_reg[1:0]. Examine the synthesis output to determine the exact binary encoding Yosys applied to each state. Identify the physical logic consequences of relying on this default assignment for critical control paths.
Constraints
- The state register
state_regis exactly 2 bits wide. - Enum encoding strictly follows standard SystemVerilog default initialization rules.
Topics
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