SystemVerilog Unique If Enforcement

Address decoders frequently suffer from long timing paths when written as cascaded if blocks. Synthesizers infer priority logic unless instructed otherwise. By using the SystemVerilog unique if construct, designers explicitly state that the conditions are mutually exclusive. This allows the synthesizer to generate fast parallel logic and strictly traps any overlapping conditions as synthesis errors.

The address_decoder module maps an 8-bit addr bus to four distinct memory region select signals. The input address space is partitioned into four contiguous blocks. The module evaluates the address and asserts exactly one select signal while driving the others to zero.

Timing and reset rules: • This module is purely combinational. • There is no clock or reset signal. • All outputs must explicitly default to zero before the conditions are evaluated to prevent inferred latches.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | addr | input | 8 | Memory address | | sel_rom | output | 1 | Asserted when addr is between 8'h00 and 8'h3F inclusive | | sel_ram | output | 1 | Asserted when addr is between 8'h40 and 8'h5F inclusive | | sel_periph | output | 1 | Asserted when addr is between 8'h60 and 8'h7F inclusive | | sel_ext | output | 1 | Asserted when addr is between 8'h80 and 8'hFF inclusive |

Constraints

• You must use an always_comb block.
• You must use the unique if construct to evaluate the address ranges.
• Your if conditions must be explicitly mutually exclusive; checking only the upper bound will cause overlapping conditions, which unique if will intentionally flag as a synthesis error.
• Do not use case or unique case.

Topics

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