Tapped Delay Line
Digital signal processing pipelines often require time-aligning parallel data streams. A tapped delay line allows a system to access a delayed signal at multiple intermediate points rather than just the endpoint. When a synthesis tool sees a deep, untapped shift register, it typically infers a block RAM or a dedicated Shift Register LUT (SRL) primitive to save logic area. However, tapping the delay line in the middle prevents this optimization for the tapped segment, forcing the synthesizer to instantiate discrete flip-flops and significantly altering the synthesized cell count.
The solution module maintains a 16-stage, 8-bit wide delay line. Every clock cycle, a new 8-bit value enters the delay line. The module provides two continuous outputs: the value delayed by exactly 8 clock cycles, and the value delayed by exactly 16 clock cycles.
The circuit operates on the positive edge of clk. An asynchronous, active-low reset rst_n clears all 16 stages of the delay line to 0 when asserted.
Cycle 1: rst_n=0 → tap_mid=0, tap_out=0 Cycle 2: rst_n=1, d_in=8'hAA → tap_mid=0, tap_out=0 Cycle 9: rst_n=1, d_in=8'h07 → tap_mid=8'hAA, tap_out=0 Cycle 17: rst_n=1, d_in=8'h0F → tap_mid=8'h07, tap_out=8'hAA
{ "signal": [
{ "name": "clk", "wave": "p................." },
{ "name": "rst_n", "wave": "01................" },
{ "name": "d_in", "wave": "x=================", "data": ["AA", "01", "02", "03", "04", "05", "06", "07", "08", "09", "0A", "0B", "0C", "0D", "0E", "0F", "10"] },
{ "name": "tap_mid", "wave": "x=.......=........", "data": ["00", "AA"] },
{ "name": "tap_out", "wave": "x=...............=", "data": ["00", "AA"] }
], "head": { "text": "Data propagates through the 16-stage delay line, appearing at tap_mid after 8 cycles and tap_out after 16 cycles." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all delay stages to 0 | | d_in | input | 8 | Data input entering the delay line | | tap_mid | output | 8 | Data delayed by exactly 8 clock cycles | | tap_out | output | 8 | Data delayed by exactly 16 clock cycles |
Constraints
- Circuit must trigger on the positive edge of
clk. - Reset must be asynchronous and active-low.
- On reset, all 16 stages of the delay line must be cleared to 0.
tap_midmust output the value of the 8th delay stage.tap_outmust output the value of the 16th delay stage.- Both outputs must be registered (driven directly by flip-flops).
Topics
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