Test Point Insertion Logic
Design for Test (DFT) logic uses control points to ensure internal nodes can be sensitized and measured during manufacturing tests. The circuit implements the function Y = (A & B) ^ C with a test control point. To achieve full fault coverage, the Test_En signal must force the internal AND gate output to 1 when asserted.
Expected behavior:
| Test_En | A | B | C | Y | |-----------|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | 0 |
Automatic Test Pattern Generation (ATPG) simulation fails. The test vector Test_En=1, A=0, B=0, C=0 outputs Y=0 instead of 1. The control point fails to sensitize the downstream logic. Inspect the circuit and correct the fault.
Constraints
- Do not alter the fundamental logic path for
Test_En = 0. - Use exactly one logic gate to inject the
Test_Encontrol signal.
Topics
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