The Broken Pipelined Multiplier
A 2-bit pipelined multiplier computes the product of two 2-bit inputs A and B, delivering the 4-bit result P after a one-cycle pipeline delay to maximize clock frequency.
Expected behavior:
When a sequence of inputs is applied, the correct product appears on the output P in the following clock cycle.
| Cycle | A | B | Expected P | |-------|-----|-----|--------------| | 1 | 1 | 1 | 0 | | 2 | 3 | 3 | 1 | | 3 | 0 | 0 | 9 | | 4 | 0 | 0 | 0 |
Simulation shows P = 3 in cycle 2 and P = 6 in cycle 3. The output is incorrect when inputs change on consecutive clock cycles. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output port definitions.
- Add or replace components only on the existing data paths.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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