The Deeply Nested Latch
A nested data router multiplexes three data sources based on enable and mode signals for an arithmetic logic unit.
Expected behavior:
The circuit must implement purely combinational routing: * When En = 0, Out = 0. * When En = 1 and Mode = 0, Out = C. * When En = 1, Mode = 1, and Sel = 1, Out = A. * When En = 1, Mode = 1, and Sel = 0, Out = B.
Simulation test sequences reveal unintended state-holding behavior. When inputs transition from En=1, Mode=1, Sel=1, A=1 to En=1, Mode=1, Sel=0, B=0, the output Out remains 1 instead of updating to 0. The router fails to evaluate the lowest branch of the logic tree correctly. Inspect the circuit and correct the fault.
Constraints
- Do not add any flip-flops or clock signals.
- Ensure the final circuit is purely combinational with no feedback loops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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