The Gated Clock Trap
A clock gating cell selectively passes a clock signal to sequential logic to reduce dynamic power consumption.
Expected behavior:
| Step | CLK | EN | GCLK | Notes | |------|-------|------|--------|-------| | 1 | 0 | 0 | 0 | Clock low, disabled | | 2 | 0 | 1 | 0 | Enable goes high | | 3 | 1 | 1 | 1 | Clock pulse begins | | 4 | 1 | 0 | 1 | Enable falls: pulse held | | 5 | 0 | 0 | 0 | Clock pulse ends |
Simulation shows GCLK = 0 during Step 4. The clock pulse is prematurely truncated. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output port definitions.
- The gating cell must not introduce glitches on the clock line.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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