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Codiode/Problems/Combinational Logic

The Self Assignment Trap

MediumLogic CircuitDebug

An error encoder generates a 2-bit status code purely from current system flags.

Expected behavior:

| clear | err_a | err_b | code | |---------|---------|---------|--------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 2 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 3 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 0 |

Synthesis reports an inferred latch on the code output. Sequential simulation shows code = 1 for input clear=0, err_a=0, err_b=0 if the preceding cycle had err_a=1. The circuit is retaining state instead of acting combinationally. Inspect the circuit and correct the fault.

Constraints

  • The circuit must be purely combinational.
  • No state retention elements or feedback loops are permitted.

Topics

VerilogCombinational RTLLatch Inference

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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