Three-Level Factored Logic vs Two-Level SOP Delay
Physical gate delay increases non-linearly with fan-in, often making wide, shallow logic trees slower than narrow, deep ones.
The schematic shows two implementations of the same Boolean function Y. Circuit A is a strict two-level Sum-of-Products (SOP) design containing a 4-input AND gate feeding into a 2-input OR gate. Circuit B is a three-level factored implementation using only 2-input AND and 2-input OR gates. Assume a 2-input gate has an intrinsic delay of 1 unit, while a 4-input gate has an intrinsic delay of 2 units.
Calculate the critical path delay for both implementations and evaluate the impact of logic depth versus gate fan-in.
Constraints
- Assume wire delay is zero.
- A 2-input logic gate introduces exactly 1 unit of delay.
- A 4-input logic gate introduces exactly 2 units of delay.
Topics
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