Tie Off Register Removal
Modern synthesis tools aggressively optimize away logic that cannot change state to save silicon area and power.
The design contains a 32-bit configuration register named cfg_mode. It is initialized to 32'h00000000 upon reset. The write enable signal cfg_we is permanently tied to 1'b0 in the top-level module, meaning the register is never written to during operation.
Analyze the synthesis outcome for cfg_mode and determine its final hardware footprint.
Constraints
- The register
cfg_modeis exactly 32 bits wide. - The write enable signal
cfg_weis hardwired to logic 0. - The reset value is
32'h00000000.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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