Tri State Buffer Inference
Bidirectional pins on a physical chip require specialized pad controllers to manage data flowing into and out of the device on the same physical wire. The internal logic of an ASIC or FPGA cannot use high impedance states; these states are strictly limited to the external input and output pads to prevent synthesis errors and excessive multiplexing overhead.
This module acts as a bidirectional bus transceiver. It takes an internal data signal and drives it onto the external pad only when the output enable signal is asserted. When the output enable is deasserted, the module releases the pad by driving it to a high impedance state, allowing external devices to drive the bus. Simultaneously, the module continuously monitors the pad and routes its current logic level to an internal input data signal, regardless of who is driving the bus.
This is a purely combinational circuit. There are no clocks, resets, or registers.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | pad | inout | 8 | Bidirectional external bus pad | | data_out | input | 8 | Internal data to drive onto the pad | | out_en | input | 1 | Active high output enable; drives pad when 1 | | data_in | output | 8 | Internal data received from the pad |
Constraints
- Purely combinational logic; no clocks or resets are used
- The
padsignal must be driven to high impedance whenout_enis 0 - The
data_insignal must continuously reflect the state ofpad - Output enable
out_enhas priority over any internal data
Topics
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