Tri State Buffer Primitive

Shared data buses require drivers that can yield control when not actively transmitting. Tri-state buffers achieve this by driving a high or low voltage when enabled, and entering a high-impedance state when disabled to avoid bus contention.

The module receives a 1-bit input signal in and a 1-bit active-high enable signal en. When en is asserted, the out signal reflects the logic level of in. When en is de-asserted, the out signal is driven to a high-impedance state (1'bz). The circuit is purely combinational.

While this behavior can be modeled with a ternary continuous assignment, Verilog provides built-in gate primitives for standard logic functions. This module must instantiate the standard bufif1 primitive to drive the output.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in | input | 1 | Data input signal | | en | input | 1 | Active-high enable signal | | out | output | 1 | Data output; driven to in when en is 1, otherwise high-impedance (z) |

Constraints

• The circuit must be purely combinational with no clocks or latches.
• The output must be exactly 1'bz when the enable signal is low.
• You must instantiate the bufif1 primitive rather than using an assign statement with a ternary operator.

Topics

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