Two-Input OR Gate Using Only Two-Input NAND Gates
Standard cell libraries often restrict available primitives to optimize silicon area and manufacturing yield. Synthesizing inclusive disjunction from a restricted set of universal gates is a fundamental mapping step in logic synthesis.
| A | B | Y | |-----|-----|-----| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 1 |
Constraints
- Use only two-input NAND gates.
- Implement the logic using a maximum of three NAND gates.
- Do not use any other logic gates or structural elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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