Undefined Opcode Latch
An arithmetic logic unit computes operations based on a 2-bit instruction code and must drive a valid deterministic output for all possible encodings.
Expected behavior:
| Op1 | Op0 | Operation | Y Output | |-------|-------|-----------|------------| | 0 | 0 | AND | A & B | | 0 | 1 | OR | A | B | | 1 | 0 | XOR | A ^ B | | 1 | 1 | Invalid | 0 |
Synthesis tools report an unintended latch on the Y output. Simulation shows that Y fails to clear to 0 when an invalid opcode is provided. For the test case Op1=1, Op0=1, A=1, B=0, the circuit holds the previous output of 1 instead of dropping to 0. Inspect the circuit and correct the fault.
Constraints
- The circuit must be strictly combinational.
- Output
Ymust be explicitly driven to0whenOp1=1andOp0=1. - Do not use flip-flops or feedback loops to retain state.
Topics
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