Unintentional Priority Logic
A memory address decoder maps a 3-bit address bus to specific device enable signals for non-overlapping memory regions.
Expected behavior:
| A2 | A1 | A0 | ROM_EN | RAM_EN | IO_EN | |------|------|------|----------|----------|---------| | 0 | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | 0 | 1 | | 1 | 1 | 1 | 0 | 0 | 1 |
Simulation shows RAM_EN = 1 and IO_EN = 1 for input A2=1, A1=1, A0=0. The RAM_EN output is incorrectly asserted, creating an unintended overlap between regions. Inspect the circuit and correct the fault.
Constraints
- Only modify the faulty logic component or wire.
- Do not change the input or output port definitions.
- The corrected circuit must evaluate all three output regions in parallel without daisy-chaining priority conditions.
Topics
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