Unreachable State Optimization
The next-state combinational logic calculates the upcoming state of a control finite state machine based on enable and mode signals.
Expected behavior:
| En | M1 | M2 | N2 | N1 | N0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | | 1 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 1 | 0 | 1 |
Simulation shows outputs N2=1, N1=0, N0=0 for input En=1, M1=1, M2=1. The transition to state 5 (101) fails and the machine incorrectly targets state 4 (100). Inspect the circuit and correct the fault.
Constraints
- Do not alter the logic paths that successfully compute states 0, 4, or 6
- Use only basic logic gates (AND, OR, NOT)
- Maintain the existing input and output port definitions
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.