Unused Flip Flop Removal
A registered datapath captures input data on the rising edge of the clock for downstream processing.
Expected behavior:
| RST | CLK | D | Q | |-------|-------|-----|-----| | 1 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 1 | | 0 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 |
Synthesis reports zero flip-flops utilized for the module. Simulation shows Q = 0 for all test cases. The circuit fails to output 1 when RST = 0, CLK = 1, and D = 1. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output port definitions.
- Do not add new logic gates or registers.
- You may only add or modify wire connections.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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