XNOR Using Only NOR Gates
Phase detectors and equality checkers rely on equivalence logic to compare digital states. Synthesizing this equivalence function using a single gate type is a standard optimization for standard-cell ASIC layouts.
Implement the logic function Y = AB + A'B' for inputs A and B.
| A | B | Y | |-----|-----|-----| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |
Constraints
- Use only 2-input NOR gates.
- Use a maximum of 4 gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.