3:8 Decoder from 2:4 Decoders
Address decoding in memory systems requires scaling small decoders into larger ones. The standard technique for multi-chip decoder expansion routes the most significant bit to the enable pins of smaller sub-decoders to partition the address space.
The circuit takes a 3-bit input (A2, A1, A0) and activates exactly one of eight output lines (Y0 through Y7).
| A2 | A1 | A0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 | |------|------|------|------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Constraints
- Implement the logic using exactly two 2:4 decoders with active-high enable (
EN) pins. - Use exactly one NOT gate.
- Do not use discrete AND/OR logic gates to perform the decoding.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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