Debug 2:4 Decoder Enable Polarity
A 2-to-4 line decoder with an active-high enable routes a single active signal to one of four output lines based on a 2-bit address.
Expected behavior:
| EN | A1 | A0 | Y3 | Y2 | Y1 | Y0 | |------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Simulation shows Y0 = 1 for input EN=0, A1=0, A0=0. Furthermore, all outputs remain 0 when EN=1. The decoder activates when it should be disabled and disables when it should be active. Inspect the circuit and correct the fault.
Constraints
- Do not alter the core decoding logic gates.
- Ensure the circuit uses standard logic gates to route the enable signal correctly.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.