4-Bit 2's Complement Adder/Subtractor
Arithmetic logic units compute both addition and subtraction using the same datapath to save silicon area. A unified adder/subtractor block conditionally negates one operand and leverages the carry-in bit to complete a two's complement conversion in a single pass.
The circuit computes A + B when mode is 0, and A - B when mode is 1. The operation uses two's complement arithmetic to perform the subtraction.
| mode | Operation | S | Cout | |--------|-----------|-----|--------| | 0 | Add | A + B | Carry from MSB | | 1 | Subtract | A - B | Carry from MSB |
Constraints
- Combinational logic only.
- Use exactly one 4-bit adder structure.
- Do not instantiate separate dedicated adder and subtractor blocks multiplexed together.
- Derive the subtraction using two's complement arithmetic on the
Binput.
Topics
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