Debug 2-Bit Adder/Subtractor
A programmable adder/subtractor is the core arithmetic unit in any basic ALU.
Expected behavior:
The circuit computes a 2-bit addition (Sum = A + B) when Mode = 0 and a 2-bit two's complement subtraction (Sum = A - B) when Mode = 1.
Simulation shows that all addition operations pass, but subtraction operations produce results that are exactly one less than expected. For example, testing A = 2 (A1=1, A0=0), B = 1 (B1=0, B0=1), and Mode = 1 yields output S1=0, S0=0 instead of the correct S1=0, S0=1. Inspect the circuit and correct the fault.
Constraints
- Do not replace the existing full adder components.
- Modify only the incorrect routing to restore full functionality.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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