4-Bit Equality Comparator
Address decoders and content-addressable memory cells frequently check if two values match exactly. When relative magnitude is irrelevant, deploying a full magnitude comparator wastes silicon area and increases propagation delay.
The circuit compares two 4-bit inputs, A and B. The output Eq asserts high if and only if every bit of A exactly matches the corresponding bit of B.
| A | B | Eq | |-----|-----|------| | 0000| 0000| 1 | | 0101| 0101| 1 | | 1111| 1111| 1 | | 1000| 0000| 0 | | 0110| 0111| 0 |
Constraints
- Implement the logic using exactly four 2-input XNOR gates and one 4-input AND gate.
- Do not generate greater-than or less-than signals.
- Use only combinational logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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