Build a 4-Bit Magnitude Comparator Using Cascaded 1-Bit Stages
Microprocessors and sorting accelerators rely on magnitude comparators to evaluate branching conditions and data relationships. Constructing arbitrary-width comparators requires chaining modular fixed-width stages via cascade signals.
The circuit compares two 4-bit unsigned numbers, A[3:0] and B[3:0]. It produces three 1-bit outputs: Gt for A > B, Eq for A == B, and Lt for A < B. The design evaluates the numbers from the least significant bit (LSB) to the most significant bit (MSB). Each 1-bit stage compares its respective bits of A and B alongside the cascade inputs from the previous, less significant stage.
The LSB stage has no preceding comparator. Its cascade inputs must be initialized to a baseline state representing mathematical equality:
| Gt_in | Eq_in | Lt_in | |---------|---------|---------| | 0 | 1 | 0 |
The cascade outputs of the MSB stage serve as the final Gt, Eq, and Lt outputs for the entire 4-bit circuit.
Constraints
- Instantiate exactly four 1-bit comparator stages.
- Connect the stages in a ripple-cascade configuration from LSB to MSB.
- Tie the LSB cascade inputs to the exact constant values specified in the description.
- Use only combinational logic.
Topics
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