8-to-1 Multiplexer via Case Statement
Data routing networks in digital processors rely heavily on wide parallel multiplexers to select operands for the ALU or to route data onto shared buses. When synthesizing these data paths, engineers use case statements to cleanly infer parallel multiplexers without the priority routing logic that cascaded conditional statements generate.
The module routes one of eight 8-bit input buses to a single 8-bit output bus. A 3-bit select signal determines which input is passed through to the output.
This circuit is purely combinational. The output updates immediately whenever the select signal or any of the input buses change. There is no clock and no reset.
| Signal | Direction | Width | Description | |---|---|---|---| | sel | input | 3 | Select signal determining which input bus is routed to the output | | d0 | input | 8 | Data input selected when sel is 3'b000 | | d1 | input | 8 | Data input selected when sel is 3'b001 | | d2 | input | 8 | Data input selected when sel is 3'b010 | | d3 | input | 8 | Data input selected when sel is 3'b011 | | d4 | input | 8 | Data input selected when sel is 3'b100 | | d5 | input | 8 | Data input selected when sel is 3'b101 | | d6 | input | 8 | Data input selected when sel is 3'b110 | | d7 | input | 8 | Data input selected when sel is 3'b111 | | y | output| 8 | Selected data output |
Constraints
- The circuit must be purely combinational.
- No latches may be inferred.
- All possible values of
selmust be explicitly handled. - The output
ymust reflect the selected input without any clock delay.
Topics
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