Cascaded 4-to-1 Multiplexer
FPGA architectures often provide native 2-to-1 multiplexers within their logic cells. Synthesizing wider data selection buses requires cascading these foundational primitives into a larger routing tree. The solution module acts as a 4-to-1 multiplexer, routing one of four 1-bit data inputs to a single output based on a 2-bit select signal.
Instead of using behavioral Verilog constructs like a case statement, this module must be structurally constructed by instantiating exactly three 2-to-1 multiplexers. A pre-defined module named mux2to1 is provided for this purpose.
The mux2to1 module has the following ports: • a: 1-bit input (selected when s is 0) • b: 1-bit input (selected when s is 1) • s: 1-bit select input • y: 1-bit data output
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | d0 | input | 1 | Data input 0; routed to y when sel is 2'b00 | | d1 | input | 1 | Data input 1; routed to y when sel is 2'b01 | | d2 | input | 1 | Data input 2; routed to y when sel is 2'b10 | | d3 | input | 1 | Data input 3; routed to y when sel is 2'b11 | | sel | input | 2 | Select signal; sel[1] is the MSB, sel[0] is the LSB | | y | output | 1 | Selected data output |
Constraints
- The design must be purely combinational.
- You must structurally instantiate the provided
mux2to1module exactly three times. - You may not use
assign y = ...for the final 4-to-1 selection logic. - Select signal
sel[1]is the most significant bit;sel[0]is the least significant bit.
Topics
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