8:3 Priority Encoder from 4:2 Encoders
Interrupt controllers and bus arbiters rely on priority encoders to identify the highest-ranking request among multiple devices. Large encoders are constructed hierarchically by cascading smaller standard encoder blocks.
The circuit accepts eight request lines D7 through D0 and outputs a 3-bit index Y2, Y1, Y0 of the highest asserted input, alongside an overall valid signal V. D7 holds the highest priority. The upper 4:2 encoder evaluates D7 through D4. The lower 4:2 encoder evaluates D3 through D0.
When the upper encoder's valid output is 1, its 2-bit code drives the lower two bits of the final output and the most significant bit Y2 is set to 1. When the upper encoder's valid output is 0, the lower encoder provides the lower two bits and Y2 is set to 0. The overall valid signal V asserts if any input bit is high.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Y2 | Y1 | Y0 | V | |------|------|------|------|------|------|------|------|------|------|------|-----| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | X | X | X | X | X | X | X | 1 | 1 | 1 | 1 | | 0 | 1 | X | X | X | X | X | X | 1 | 1 | 0 | 1 | | 0 | 0 | 0 | 0 | 1 | X | X | X | 0 | 1 | 1 | 1 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
Constraints
- Use exactly two 4:2 priority encoder blocks.
- Use a multiplexer to route the correct 2-bit code to
Y1andY0. - Combinational logic only.
Topics
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