Accumulator Feedback Multiplexer

Digital signal processing blocks in FPGAs and ASICs often feature dedicated adders and registers, but their internal flip-flops may lack a synchronous clear pin. When an accumulator needs to be periodically reset, relying on the register's reset pin can force the synthesis tool to pull the logic out of the dedicated DSP slice and into slower, general-purpose fabric. A more optimal approach is to clear the accumulator by multiplexing a zero into the adder's feedback path, allowing the register to simply clock in the zero on the next cycle.

The module maintains a running sum of incoming 8-bit data values. On each clock cycle where the enable signal is asserted, the current input is added to the accumulated total. When the synchronous clear signal is asserted, the feedback loop from the accumulator register to the adder is broken. Instead of adding the input to the previous sum, the circuit adds the input to zero, effectively restarting the accumulation from the current input value on that exact cycle.

• Clock edge: posedge
• Reset type: Asynchronous active-low (rst_n)
• Reset polarity: The output register goes to 0 when rst_n is 0.
• Clear behaviour: Synchronous active-high (sync_clear). When sync_clear is 1, the feedback operand to the internal adder becomes 0.
• Enable behaviour: Synchronous active-high (valid). The accumulator only updates its state when valid is 1. If valid is 0, the accumulator holds its previous value, completely ignoring both sync_clear and data_in.

Cycle 1: rst_n=0 • acc_out=0 Cycle 2: rst_n=1, valid=1, sync_clear=0, data_in=5 • acc_out=0 Cycle 3: valid=1, sync_clear=0, data_in=3 • acc_out=5 Cycle 4: valid=0, sync_clear=1, data_in=10 • acc_out=8 Cycle 5: valid=1, sync_clear=1, data_in=4 • acc_out=8 (held due to valid=0 in previous cycle) Cycle 6: valid=1, sync_clear=0, data_in=2 • acc_out=4 (feedback was 0 in previous cycle) Cycle 7: valid=0, sync_clear=0, data_in=0 • acc_out=6

{ "signal": [
  { "name": "clk",        "wave": "p......" },
  { "name": "rst_n",      "wave": "01....." },
  { "name": "valid",      "wave": "0110110" },
  { "name": "sync_clear", "wave": "0001100" },
  { "name": "data_in",    "wave": "x======x", "data": ["5", "3", "10", "4", "2", "0"] },
  {},
  { "name": "acc_out",    "wave": "2.22.22", "data": ["0", "5", "8", "4", "6"] }
], "head": { "text": "Cycle-by-cycle accumulator behaviour." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; sets acc_out to 0 | | valid | input | 1 | Register enable; accumulator updates only when valid is 1 | | sync_clear | input | 1 | Synchronous clear; forces the adder's feedback operand to 0 | | data_in | input | 8 | Input data to be accumulated | | acc_out | output | 16 | Accumulated sum; resets to 16'b0 |

Constraints

• Clock edge must be posedge clk.
• Reset must be asynchronous and active-low.
• The output acc_out must be exactly 16 bits wide.
• Overflow behaviour is standard truncation; the sum wraps around naturally if it exceeds 16 bits.
• The valid signal has strict priority over sync_clear; if valid is 0, the register state does not change under any circumstance.
• Do not evaluate sync_clear inside the sequential block's reset or enable logic; it must operate as a data-path multiplexer feeding the combinational adder.

Topics

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