ALU Less Than Flag Logic
Modern processors avoid dedicating silicon to standalone comparators. Instead, they evaluate branching conditions by performing a subtraction and analyzing the resulting condition flags.
Derive the signed Less Than (LT) condition for an instruction like CMP A, B using only the Negative (N) and Overflow (V) flags generated by the A - B operation. The output LT must assert when operand A is strictly less than operand B in two's complement representation.
| N | V | LT | |-----|-----|------| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Constraints
- Combinational logic only.
- Implement using basic logic gates.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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