Always FF Edge Strictness
A standard D flip-flop with asynchronous reset forms the foundational state-holding element in synchronous digital designs. This particular instance sits at the output of a reset tree where the reset is distributed asynchronously across multiple clock domains. The block uses SystemVerilog's always_ff construct, which enforces stricter simulation semantics than the Verilog always block.
The solution module captures d on each rising clock edge and drives q. The reset rst_n is active-low and asynchronous. Asserting rst_n low must drive q to 0 immediately regardless of the clock.
Compilation fails with a semantic error during elaboration. The compiler flags the sequential block for violating always_ff strictness rules. Inspect the module and correct the fault.
| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; q goes to 0 immediately when asserted | | d | input | 1 | Data input captured on rising clock edge | | q | output | 1 | Registered output; resets to 0 |
Constraints
- Clock is positive-edge triggered.
- Reset is asynchronous and active-low;
qmust go to 0 immediately whenrst_nis low. - The module must use the
always_ffkeyword. - Output
qis registered.
Topics
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