Always Latch Intentional Design

Clock distribution networks consume significant power in modern hardware. To save power, entire functional blocks are disabled by turning off their clocks. However, simply ANDing an enable signal with the clock creates dangerous glitches if the enable transitions while the clock is high. Integrated Clock Gating (ICG) cells solve this by safely synchronizing the enable signal using a latch.

The module receives a master clock clk, a functional enable en, and a test enable te. It outputs a gated_clk. To prevent glitches, the combined enable (en OR te) must be latched while clk is low. The latched enable is then ANDed with clk to produce gated_clk. Because latches are typically considered design errors, synthesis tools warn when they are inferred. SystemVerilog provides the always_latch block to explicitly declare intentional latch inference.

• Clock edge: The latch is transparent when clk is low (level-sensitive, not edge-triggered).
• Reset: There is no dedicated reset pin. The latch initializes its state during the low phase of clk.
• Combinational logic: The enable condition is en OR te.
• Output: gated_clk is the logical AND of clk and the latched enable.

Cycle 1 (clk=0): en=1, te=0 → latched enable=1, gated_clk=0 Cycle 2 (clk=1): en=0, te=0 → latched enable=1 (hold), gated_clk=1 Cycle 3 (clk=0): en=0, te=0 → latched enable=0, gated_clk=0 Cycle 4 (clk=1): en=1, te=0 → latched enable=0 (hold), gated_clk=0

{ "signal": [
  { "name": "clk",       "wave": "0101" },
  { "name": "en",        "wave": "1001" },
  { "name": "te",        "wave": "0..." },
  {},
  { "name": "latched_en","wave": "1.0." },
  { "name": "gated_clk", "wave": "010." }
], "head": { "text": "Glitch-free clock gating cell preventing glitches on the output." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Master clock and active-low latch enable | | en | input | 1 | Functional clock enable | | te | input | 1 | Test enable; forces clock on for DFT | | gated_clk | output | 1 | Gated clock output |

Constraints

• Must use the SystemVerilog always_latch keyword.
• The latch must be transparent when clk is 0.
• Output gated_clk must be driven by an AND gate.
• Do not use edge-triggered flip-flops.
• Do not use a reset pin.

Topics

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