Array of Interfaces for Arbitration
High-performance SoCs often feature multiple initiators competing for a single shared resource, such as a memory controller or an egress network port. Hardcoding individual ports for every initiator creates brittle code. Instead, designers use arrays of interfaces to scale arbitration logic systematically.
This module acts as a 4-to-1 round-robin arbiter for an array of four AXI-Stream-like connections. It takes an array of four input interfaces (represented as packed arrays for valid, ready, and data) and multiplexes them to a single output interface. You will dynamically route these signals using a generate loop or a combinational for loop, ensuring the design scales cleanly. The arbiter grants access to one active input at a time based on a rotating priority scheme. When an input is granted, its data and valid signals are routed to the output, and the output's ready signal is routed back to that specific input.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | in_valid | input | 4 | Array of valid signals from the 4 requestors | | in_data | input | 4x32 | Array of four 32-bit data buses ([3:0][31:0]) | | in_ready | output | 4 | Array of ready signals routed back to the requestors | | out_valid | output | 1 | Multiplexed valid signal to the target | | out_ready | input | 1 | Ready signal from the target | | out_data | output | 32 | Multiplexed 32-bit data to the target |
Worked Trace: Cycle 1: rst_n=0 → priority pointer=0, out_valid=0, in_ready=4'b0000 Cycle 2: rst_n=1, in_valid=4'b0001, out_ready=1 → Port 0 wins. out_valid=1, in_ready=4'b0001, out_data=in_data[0]. Handshake completes, priority updates to 1. Cycle 3: in_valid=4'b0011, out_ready=1 → Priority is 1, so Port 1 wins. out_valid=1, in_ready=4'b0010, out_data=in_data[1]. Handshake completes, priority updates to 2. Cycle 4: in_valid=4'b0100, out_ready=0 → Priority is 2, Port 2 wins. out_valid=1, in_ready=4'b0000 (since out_ready=0), out_data=in_data[2]. No handshake, priority holds at 2.
Constraints
- Positive-edge triggered
clk. - Asynchronous active-low
rst_n. - On reset, the priority pointer must initialize to input 0.
- During reset (
rst_n= 0),out_validmust be 0 and all bits ofin_readymust be 0, regardless of input values. - When no inputs are valid,
out_validmust be 0 andout_datamust be driven to 0. - The priority pointer updates to
granted_index + 1(wrapping around to 0 after 3) exactly on the cycle after a successful handshake (out_valid== 1 andout_ready== 1). - The
in_readyarray must only assert for the granted input; all otherin_readybits must be 0. - Output routing (
out_valid,out_data, and the inputreadyarray) must be strictly combinational based on the current priority pointer and inputs.
Topics
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