Asymmetric Clock Divider

High-speed communication interfaces often require internal clock frequencies that are non-binary fractions of the main system clock. Generating an odd-integer divided clock with a perfect 50% duty cycle is critical for double-data-rate (DDR) registers that sample on both the rising and falling edges.

Design a clock divider module that divides the input clock frequency by exactly 3. Unlike a standard counter-based divider which inherently yields a 33% or 66% duty cycle, this circuit must produce a perfect 50% duty cycle. To achieve this, the output waveform must transition on both the rising and falling edges of the source clock.

The module uses an asynchronous active-low reset. When the reset is asserted, the output clock must immediately go low. When the reset is released, the first rising edge of the divided clock must occur exactly on the first rising edge of the input clock.

Timing and Reset Rules: • Clock edge: Both posedge clk and negedge clk are required to achieve the 50% duty cycle. • Reset type: Asynchronous. • Reset polarity: Active-low (rst_n). • Output values on reset: clk_out goes to 0 immediately when rst_n is 0.

Worked Trace: Each step represents a half-cycle of the input clock. • Half-Cycle 1 (clk=0): rst_n=0 → clk_out=0 • Half-Cycle 2 (clk=1): rst_n=0 → clk_out=0 • Half-Cycle 3 (clk=0): rst_n=1 → clk_out=0 (Reset released) • Half-Cycle 4 (clk=1): rst_n=1 → clk_out=1 (First posedge after reset) • Half-Cycle 5 (clk=0): rst_n=1 → clk_out=1 • Half-Cycle 6 (clk=1): rst_n=1 → clk_out=1 • Half-Cycle 7 (clk=0): rst_n=1 → clk_out=0 (Output falls on negedge) • Half-Cycle 8 (clk=1): rst_n=1 → clk_out=0 • Half-Cycle 9 (clk=0): rst_n=1 → clk_out=0 • Half-Cycle 10 (clk=1): rst_n=1 → clk_out=1 (Output rises on posedge, pattern repeats)

{ "signal": [
  { "name": "clk",     "wave": "010101010101010101" },
  { "name": "rst_n",   "wave": "001111111111111111" },
  { "name": "clk_out", "wave": "000111000111000111" }
], "head": { "text": "Each step represents a half-cycle of the input clock." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Source clock | | rst_n | input | 1 | Asynchronous active-low reset; clk_out goes to 0 when asserted | | clk_out | output | 1 | Divided-by-3 clock with exactly 50% duty cycle |

Constraints

• The circuit must use both the positive and negative edges of the input clock.
• The output clk_out must maintain a strict 50% duty cycle (high for exactly 1.5 input cycles, low for exactly 1.5 input cycles).
• The output clk_out must transition to 1 on the very first posedge clk after rst_n is de-asserted.
• All internal state must be properly initialized by the asynchronous reset.

Topics

Related problems

• Basic D Flip FlopEasy
• Debug: Missing Edge in Sensitivity ListMedium
• Read After Write Hazard DetectionEasy
• Parameterized Interface with ModportsHard
• Struct Array PipelineHard
• T Flip Flop from D Flip Flop TemplateEasy
• Recursive Generate Reduction TreeHard
• Four Stage Shift RegisterEasy