Asynchronous Reset Inference

Standard cell libraries provide flip-flops with dedicated asynchronous reset pins, allowing registers to be cleared independently of the clock signal. This ensures the system can be initialized safely upon power-up or recovered from an error state even if the system clock is stopped, unstable, or gated off.

The module acts as an 8-bit register. It captures the value of the d input and drives it to the q output on the active clock edge. When the reset signal is asserted, the output immediately goes to 0, completely bypassing the clock. Synthesis tools like Yosys will infer a flip-flop with a dedicated CLR port only if the hardware description explicitly describes this asynchronous priority relationship.

• Clock edge: posedge
• Reset type: asynchronous
• Reset polarity: active-low
• Output values on reset: q is forced to 8'h00
• Priority rules: rst_n being low takes absolute priority over any clock edge or data input

Worked Trace: Cycle 1: rst_n=0, clk=0, d=8'hAA → q=8'h00 (Async reset holds output at 0 without a clock) Cycle 2: rst_n=1, clk=1, d=8'hAA → q=8'hAA (Normal capture on posedge) Cycle 3: rst_n=1, clk=1, d=8'h55 → q=8'h55 (Normal capture on posedge) Cycle 4: rst_n=0, clk=0, d=8'hFF → q=8'h00 (Async reset clears output immediately mid-cycle)

{ "signal": [
  { "name": "clk",   "wave": "0101010" },
  { "name": "rst_n", "wave": "0.1...0" },
  { "name": "d",     "wave": "==.=.==", "data": ["AA", "AA", "55", "FF", "FF"] },
  {},
  { "name": "q",     "wave": "==.=.==", "data": ["00", "AA", "55", "55", "00"] }
], "head": { "text": "Asynchronous reset forces output to zero independent of clock." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; forces q to 0 when asserted | | d | input | 8 | Data input to be registered | | q | output | 8 | Registered data output; resets to 8'h00 |

Constraints

• The reset must be fully asynchronous; q must update to 0 immediately when rst_n goes low, without waiting for the next clk edge
• The output q must be a registered signal updated only on the positive edge of clk when rst_n is high
• The reset signal rst_n is active-low
• The data path is exactly 8 bits wide

Topics

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