Basic Fibonacci LFSR
Pseudo-random number generators are essential in hardware for data scrambling, cryptographic nonces, and built-in self-test (BIST) pattern generation. A Fibonacci Linear Feedback Shift Register (LFSR) provides a lightweight, high-speed pseudo-random sequence using a simple shift register and XOR gates to generate feedback.
The module computes the next state of an 8-bit sequence. On each active clock edge where the enable signal is asserted, the register shifts its contents left by one position (from least significant to most significant). The new least significant bit is populated by the XOR sum of specific tap bits from the current state. Because an LFSR constructed with XOR gates will lock up permanently if it ever reaches an all-zeros state, the module continuously monitors the register. If an all-zeros state is detected, the register must immediately overwrite its contents with a recovery seed on the next enabled clock cycle.
- Clock edge:
posedge - Reset type: Asynchronous
- Reset polarity: Active-low
- Output on reset:
8'h01 - Shift direction: Left (
lfsr_out[7:1]receiveslfsr_out[6:0]) - Feedback taps: Bits
7,5,4, and3(0-indexed) - Lockup recovery: If
lfsr_out == 8'h00anden == 1, the next state becomes8'h01 - Priority: Reset has the highest priority; lockup recovery takes precedence over standard shifting.
Worked Trace: Cycle 1: rst_n=0 → lfsr_out=8'h01 Cycle 2: rst_n=1, en=1 → feedback = 0^0^0^0 = 0. Shift left: 8'h01 << 1 = 8'h02. lfsr_out=8'h02 Cycle 3: en=1 → feedback = 0^0^0^0 = 0. lfsr_out=8'h04 Cycle 4: en=0 → lfsr_out=8'h04 (hold) Cycle 5: en=1 → feedback = 0^0^0^0 = 0. lfsr_out=8'h08 Cycle 6: en=1 → taps [7]=0, [5]=0, [4]=0, [3]=1. feedback = 1. lfsr_out=8'h11
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "en", "wave": "01.011." },
{ "name": "lfsr_out", "wave": "=.=====", "data": ["01", "02", "04", "04", "08", "11"] }
], "head": { "text": "Basic shift and enable hold behavior." } }| Signal | Direction | Width | Description | |------------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; output goes to 8'h01 when asserted | | en | input | 1 | Enable; register shifts or recovers on posedge clk while en=1 | | lfsr_out | output | 8 | Current LFSR state; resets to 8'h01 |
Constraints
- All outputs must be registered on the positive edge of
clk - The module must strictly use 0-indexed tap bits
7,5,4, and3for the XOR feedback - The lockup recovery seed must be exactly
8'h01 - The LFSR must shift left, meaning the XOR feedback bit is shifted into bit
0
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.