Basic Replication Operator
Hardware designs frequently require sign-extension or the broadcast of a single control signal across a wide bus. Writing out manual concatenations for these duplicated bits is tedious and prone to human error. The Verilog replication operator provides a concise way to duplicate a single bit or a sequence of bits multiple times.
This module takes a single input bit and duplicates it to form an 8-bit output vector. When the input is a logical zero, the output becomes all zeros. When the input is a logical one, the output becomes all ones.
The circuit is purely combinational. There is no clock or reset signal. The output must update immediately when the input changes.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in_bit | input | 1 | Single bit to be replicated | | out_vec | output | 8 | Eight-bit vector containing the replicated input bit |
Constraints
- The design must be purely combinational logic
- The output
out_vecmust consist exactly of thein_bitrepeated eight times - No sequential elements or flip-flops are permitted
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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