Build a 4:1 MUX from Three 2:1 MUXes
Large routing networks in processors and memory controllers rely on hierarchical selection structures rather than flat gate-level designs. Cascading smaller multiplexers into trees creates scalable data paths with uniform propagation delays.
Construct a 4:1 multiplexer that routes one of four data inputs (I0, I1, I2, I3) to the output Y based on a 2-bit select signal (S1, S0). The signal S1 serves as the most significant bit of the selector.
| S1 | S0 | Y | |------|------|-----| | 0 | 0 | I0| | 0 | 1 | I1| | 1 | 0 | I2| | 1 | 1 | I3|
Constraints
- Construct the circuit using exactly three 2:1 multiplexers.
- Do not use any basic logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR).
- Route the select lines so that all combinations correctly map the inputs to the output.
Topics
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