Build an 8:1 MUX from Seven 2:1 MUXes in a 3-Level Tree
High-capacity data routing in ALUs and memory subsystems relies on cascading smaller multiplexers into larger trees. A 3-level tree scales a fundamental 2:1 selection element to route one of eight data sources to a single destination.
The output Y must match the data input D0 through D7 selected by the 3-bit control bus formed by S2, S1, and S0. The signal S2 acts as the most significant bit of the selection index, and S0 acts as the least significant bit.
| S2 | S1 | S0 | Y | |------|------|------|-----| | 0 | 0 | 0 | D0| | 0 | 0 | 1 | D1| | 0 | 1 | 0 | D2| | 0 | 1 | 1 | D3| | 1 | 0 | 0 | D4| | 1 | 0 | 1 | D5| | 1 | 1 | 0 | D6| | 1 | 1 | 1 | D7|
Constraints
- Use exactly seven 2:1 multiplexers.
- Do not use any higher-order multiplexer components.
- Use only combinational logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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