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Codiode/Problems/Combinational Logic

Build the Circuit for F = (A+B)(C+D)(E+F) Under a Two-Input Gate Constraint

MediumLogic CircuitBuild

Standard cell libraries restrict gate fan-in to guarantee predictable timing and layout area. Complex Boolean equations must often be mapped to a cascade of simpler two-input primitives.

The circuit must evaluate the Product of Sums (POS) expression: Y = (A + B) * (C + D) * (E + F). The output is labeled Y to avoid confusion with the input F. The circuit evaluates to 1 only when at least one input in every pair is 1.

| A | B | C | D | E | F | Y | |-----|-----|-----|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | 1 | 1 | 1 | 1 |

Constraints

  • Use only two-input logic gates.
  • Combinational logic only.

Topics

Gate-Level LogicFan-inStandard Cells

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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