Shared Subexpression: F1 = AB + C, F2 = AB + D
Synthesis tools routinely identify common logic across multiple outputs to minimize area and power. Computing the same boolean product multiple times wastes standard cells and routing resources.
Implement two boolean functions, F1 and F2, driven by four inputs: A, B, C, and D. Both functions share a common product term.
F1 = (A AND B) OR C F2 = (A AND B) OR D
| A | B | C | D | F1 | F2 | |-----|-----|-----|-----|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 0 | 1 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 1 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 | 1 | 1 |
Constraints
- Use exactly one AND gate.
- Use exactly two OR gates.
- Do not use any other logic gates.
- The output of the AND gate must fan out to drive an input on both OR gates.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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