Clock and Reset Generation Testbench

Every robust verification environment relies on a precise clock and reset generator. Incorrect clock generation or misaligned reset timing in a testbench hides setup and hold violations, potentially leading to silicon failure. The foundational step in building any sequential testbench is generating these signals autonomously with exact timing.

The module acts as a testbench generator block. It must autonomously produce a 100 MHz clock signal and an active-low asynchronous reset. The reset must be asserted at the very beginning of the simulation to initialize downstream logic. To ensure clean recovery timing and avoid race conditions, the reset must cleanly deassert exactly on a falling clock edge.

Timing and reset rules: • The module requires no inputs; it uses time delays to drive its outputs. • A 100 MHz clock corresponds to a 10 ns period. • At time t = 0, clk must initialize to 1 and rst_n must initialize to 0. • clk must toggle every 5 ns. • rst_n must remain asserted (0) for exactly 25 ns. • At exactly t = 25 ns, rst_n must deassert (1). This coincides exactly with the third falling edge of clk.

Worked trace of the expected timing: t = 0 ns: clk=1, rst_n=0 t = 5 ns: clk=0, rst_n=0 (first falling edge) t = 10 ns: clk=1, rst_n=0 (first rising edge) t = 15 ns: clk=0, rst_n=0 (second falling edge) t = 20 ns: clk=1, rst_n=0 (second rising edge) t = 25 ns: clk=0, rst_n=1 (third falling edge; reset cleanly deasserts) t = 30 ns: clk=1, rst_n=1 (third rising edge)

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | output | 1 | 100 MHz clock signal; initializes to 1 at t=0 | | rst_n | output | 1 | Active-low asynchronous reset; initializes to 0, deasserts to 1 at t=25 ns |

Constraints

• clk must maintain an exact 10 ns period (100 MHz).
• clk must start at 1 at t = 0.
• rst_n must start at 0 at t = 0 and transition to 1 at exactly t = 25 ns.
• The module has no inputs; you must use initial and always blocks with time delays (#) to generate the signals.

Topics

Related problems

• Basic D Flip FlopEasy
• Debug: Missing Edge in Sensitivity ListMedium
• Read After Write Hazard DetectionEasy
• Parameterized Interface with ModportsHard
• Struct Array PipelineHard
• T Flip Flop from D Flip Flop TemplateEasy
• Recursive Generate Reduction TreeHard
• Four Stage Shift RegisterEasy