Clock Divider Metastability
Ripple counters consume very little power but introduce significant timing risks when interfacing with synchronous logic. The circuit below features a primary clock CLK operating at 125 MHz. CLK drives the clock pin of FF0. The output of FF0 clocks FF1, and the output of FF1 clocks FF2, forming a three-stage ripple counter. The final stage FF2 generates a signal DATA_OUT that is sampled by FF3, which operates directly on the primary CLK domain. All flip-flops share identical characteristics: a clock-to-Q delay of 2.5ns and a setup time of 1.0ns. Trace the cumulative delay through the ripple stages and determine the timing margins at FF3.
Constraints
CLKfrequency is 125 MHz.- Clock-to-Q delay is 2.5ns for all flip-flops.
- Setup time is 1.0ns for all flip-flops.
- Combinational delay between all stages is 0ns.
Topics
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